TY - JOUR
T1 - Toward increasing FPGA lifetime
AU - Srinivasan, Suresh
AU - Krishnan, Ramakrishnan
AU - Mangalagiri, Prasanth
AU - Xie, Yuan
AU - Narayanan, Vijaykrishnan
AU - Irwin, Mary Jane
AU - Sarpatwari, Karthik
N1 - Funding Information:
This work was supported in part by grants from DARPA, MARCO, and GSRC, and by US National Science Foundation CAREER: Compiling for Energy Award 0093085 and NSF Grants 0202007 and 0454123. This work was published in DAC 2006 and presented here with enhanced reliability analysis.
Funding Information:
Mary Jane Irwin received the MS and PhD degrees in computer science from the University of Illinois, Urbana-Champaign, in 1975 and 1977, respectively. She has been on the faculty at Pennsylvania State University, University Park, since 1977 and currently holds the title of Evan Pugh Professor and A. Robert Noll Chair in Engineering in the Department of Computer Science and Engineering. Her re-search and teaching interests include computer architecture, embedded and mobile computing systems design, and power-aware and reliable systems design. Her research is supported by grants from the MARCO Gigascale Systems Research Center, the National Science Foundation, and the Semiconductor Research Corp. She is currently serving as the co-editor in chief of the ACM Journal of Emerging Technologies in Computing Systems. She received an Honorary Doctorate from Chalmers University of Technology, Goteborg, Sweden, in 1997. She was elected to the National Academy of Engineering in 2003. She is currently serving as a cochair of ACM’s Publication Board and is on the steering committee of CRA’s Committee on the Status of Women in Computing Research. She is a fellow of the IEEE and the ACM.
PY - 2008
Y1 - 2008
N2 - Field-Programmable Gate Arrays (FPGAs) have been aggressively moving to lower gate length technologies. Such a scaling of technology has an adverse impact on the reliability of the underlying circuits in such architectures. Various different physical phenomena have been recently explored and demonstrated to impact the reliability of circuits in the form of both transient error susceptibility and permanent failures. In this work, we analyze the impact of two different types of hard errors, namely, Time-Dependent Dielectric Breakdown (TDDB) and Electromigration (EM) on FPGAs. We also study the performance degradation of FPGAs over time caused by Hot-Carrier Effects (HCE) and Negative Bias Temperature Instability (NBTI). Each study is performed on the components of FPGAs most affected by the respective phenomena, from both the performance and reliability perspective. Different solutions are demonstrated to counter each failure and degradation phenomena to increase the operating lifetime of the FPGAs.
AB - Field-Programmable Gate Arrays (FPGAs) have been aggressively moving to lower gate length technologies. Such a scaling of technology has an adverse impact on the reliability of the underlying circuits in such architectures. Various different physical phenomena have been recently explored and demonstrated to impact the reliability of circuits in the form of both transient error susceptibility and permanent failures. In this work, we analyze the impact of two different types of hard errors, namely, Time-Dependent Dielectric Breakdown (TDDB) and Electromigration (EM) on FPGAs. We also study the performance degradation of FPGAs over time caused by Hot-Carrier Effects (HCE) and Negative Bias Temperature Instability (NBTI). Each study is performed on the components of FPGAs most affected by the respective phenomena, from both the performance and reliability perspective. Different solutions are demonstrated to counter each failure and degradation phenomena to increase the operating lifetime of the FPGAs.
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U2 - 10.1109/TDSC.2007.70235
DO - 10.1109/TDSC.2007.70235
M3 - Article
AN - SCOPUS:43649083559
SN - 1545-5971
VL - 5
SP - 115
EP - 126
JO - IEEE Transactions on Dependable and Secure Computing
JF - IEEE Transactions on Dependable and Secure Computing
IS - 2
M1 - 4384501
ER -