Transient analysis of CMOS-gate-driven RLGC interconnects based on FDTD

As the feature size of integrated circuits shrinking in deep submicron technologies, time delay, and crosstalk noise of complementary metal-oxide-semiconductor (CMOS)-gate-driven interconnects become critical issues. Traditionally, CMOS driver is simplified as a linear circuit in which a constant resistance is used to approximate the nonlinear and time-varying MOS resistance, which is inaccurate for signal integrity analysis in high-speed interconnect systems. This paper proposes a finite-difference time-domain (FDTD)-based method for transient analysis of lossy transmission lines in the presence of the nonlinear behavior of CMOS gates. The conventional FDTD with second-order accuracy is used for interconnect analysis and the parameters with frequency-dependent losses are also included. The nonlinear behavior of CMOS gates is represented by alpha-power law model, with the drain current described by piecewise linear function of the drain voltage and discretized in time domain for the FDTD implementation. Explicit forms of the boundary conditions are derived from the implicit interface equations and hence the stability is strictly constrained by Courant condition. Experimental results show that the proposed method has good accuracy and high efficiency with respect to HSPICE. Therefore, it is useful for accurate prediction of time delay and crosstalk noise in high-speed interconnect systems.