Transient analysis of CMOS-gate-driven RLGC interconnects based on FDTD

Keyphrases

• Finite-difference Time-domain 100%
• Transient Analysis 100%
• Complementary Metal Oxide Semiconductor 100%
• Gate Drive 100%
• Nonlinear Behavior 40%
• Time Delay 40%
• High-speed Interconnects 40%
• Interconnected Systems 40%
• Crosstalk Noise 40%
• High Efficiency 20%
• Integrated Circuits 20%
• Drain Current 20%
• Domain-independent 20%
• Prediction Accuracy 20%
• Discretized 20%
• Power-law Model 20%
• Good Accuracy 20%
• Second-order Accuracy 20%
• Linear Circuits 20%
• HSPICE 20%
• Piecewise Linear Function 20%
• Interconnect Analysis 20%
• Drain Voltage 20%
• Deep Submicron Technology 20%
• Alpha Power 20%
• Constant Resistance 20%
• Signal Integrity Analysis 20%
• Lossy Transmission Line 20%

Engineering

• Time Domain 100%
• Transient Analysis 100%
• Complementary Metal-Oxide-Semiconductor 100%
• Interconnects 100%
• Nonlinear Behavior 40%
• Delay Time 40%
• Crosstalk 40%
• Experimental Result 20%
• Current Drain 20%
• Feature Size 20%
• Linear Function 20%
• Accurate Prediction 20%
• Power Law Model 20%
• Good Accuracy 20%
• Explicit Form 20%
• Drain Voltage 20%
• Dependent Loss 20%
• Boundary Condition 20%
• Integrated Circuit 20%
• Lossy Transmission Line 20%
• Alpha Power 20%
• Linear Circuit 20%