TY - JOUR
T1 - Transient chip-package cosimulation of multiscale structures using the laguerre-FDTD scheme
AU - Ha, Myunghyun
AU - Srinivasan, Krishna
AU - Swaminathan, Madhavan
N1 - Funding Information:
Manuscript received June 07, 2008; revised November 10, 2008; February 01, 2009. First published July 24, 2009; current version published November 04, 2009. This work was supported by the Mixed Signal Design Tools Consortium (MSDT), Georgia Tech under Project 2126Q0R. This work was recommended for publication by Associate Editor M. Nakhla upon evaluation of the reviewers comments.
PY - 2009/11
Y1 - 2009/11
N2 - Transient simulation using Laguerre polynomials is unconditionally stable and is ideally suited for modeling structures containing both small and large feature sizes. The focus of this paper is on the automation of this technique and its application to chip-package cosimulation. Laguerre finite-difference time-domain (FDTD) requires using the right number of basis coefficients to generate accurate time-domain waveforms. A method for generating the optimal number of basis functions is presented in this paper. Equivalent circuit models of the FDTD grid have been developed. In addition, a method for simulation over a long time period is also presented that enables the extraction of the frequency response both at low and high frequencies. A node numbering scheme in the circuit model of the FDTD grid that is suitable for implementation has been discussed. Results from a chip-package example that shows the scalability of this technique to solve multiscale problems have been presented.
AB - Transient simulation using Laguerre polynomials is unconditionally stable and is ideally suited for modeling structures containing both small and large feature sizes. The focus of this paper is on the automation of this technique and its application to chip-package cosimulation. Laguerre finite-difference time-domain (FDTD) requires using the right number of basis coefficients to generate accurate time-domain waveforms. A method for generating the optimal number of basis functions is presented in this paper. Equivalent circuit models of the FDTD grid have been developed. In addition, a method for simulation over a long time period is also presented that enables the extraction of the frequency response both at low and high frequencies. A node numbering scheme in the circuit model of the FDTD grid that is suitable for implementation has been discussed. Results from a chip-package example that shows the scalability of this technique to solve multiscale problems have been presented.
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U2 - 10.1109/TADVP.2009.2020518
DO - 10.1109/TADVP.2009.2020518
M3 - Article
AN - SCOPUS:74649087403
SN - 1521-3323
VL - 32
SP - 816
EP - 830
JO - IEEE Transactions on Advanced Packaging
JF - IEEE Transactions on Advanced Packaging
IS - 4
M1 - 5173511
ER -