Skip to main navigation Skip to search Skip to main content

Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint

  • Manjit Borah
  • , Robert Michael Owens
  • , Mary Jane Irwin

Research output: Contribution to conference › Paper › peer-review

35   Link opens in a new tab Scopus citations

Fingerprint

Dive into the research topics of 'Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint'. Together they form a unique fingerprint.
Sort by

Keyphrases

Computer Science

Engineering