TY - GEN
T1 - Truncated-matrix multipliers with coefficient shifting
AU - Walters, III, Eugene George
AU - Schulte, Michael J.
PY - 2011/12/1
Y1 - 2011/12/1
N2 - Truncated-matrix multipliers offer significant reductions in area, power, and delay, at the expense of increased computational error. These tradeoffs make them an attractive choice for many signal processing systems such as FIR filters. This paper presents a method for shifting coefficients that significantly reduces the error in systems that use truncated-matrix multipliers. This method allows further reductions in area, power, and delay while maintaining the overall accuracy of the system.
AB - Truncated-matrix multipliers offer significant reductions in area, power, and delay, at the expense of increased computational error. These tradeoffs make them an attractive choice for many signal processing systems such as FIR filters. This paper presents a method for shifting coefficients that significantly reduces the error in systems that use truncated-matrix multipliers. This method allows further reductions in area, power, and delay while maintaining the overall accuracy of the system.
UR - http://www.scopus.com/inward/record.url?scp=84861317814&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84861317814&partnerID=8YFLogxK
U2 - 10.1109/ACSSC.2011.6189979
DO - 10.1109/ACSSC.2011.6189979
M3 - Conference contribution
AN - SCOPUS:84861317814
SN - 9781467303231
T3 - Conference Record - Asilomar Conference on Signals, Systems and Computers
SP - 176
EP - 180
BT - Conference Record of the 45th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2011
T2 - 45th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2011
Y2 - 6 November 2011 through 9 November 2011
ER -