TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network

Computer Science

• Networks on Chips 100%
• Power Consumption 50%
• Pipeline Stage 50%
• Verilog 50%
• Synthetic Traffic 50%
• Benchmark Program 50%

Keyphrases

• Router 100%
• Network on chip 100%
• Output Port 18%
• Router Design 18%
• Low Latency 9%
• Area Overhead 9%
• Allocation Decisions 9%
• Power Consumption 9%
• Pipeline Stages 9%
• Full-system Simulation 9%
• Synthetic Traffic 9%
• Benchmark Program 9%
• Switch Allocation 9%
• Verilog 9%
• Input Port 9%