TY - JOUR
T1 - Tunnel FET technology
T2 - A reliability perspective
AU - Datta, Suman
AU - Liu, Huichu
AU - Narayanan, Vijaykrishnan
N1 - Funding Information:
The authors would like to thank Bijesh Rajamohanan, Rahul Pandey, Matthew Cotter, Vinay Saripalli, Dheeraj Mohata for their contributions to this work. This work was supported in part by the Center for Low Energy Systems Technology (LEAST), one of the six SRC STARnet Centers, sponsored by MARCO and DARPA, and was also supported in part by the National Science Foundation (NSF) ASSIST ERC 1160483, Intel ARO and DTRA.
Copyright:
Copyright 2014 Elsevier B.V., All rights reserved.
PY - 2014/5
Y1 - 2014/5
N2 - Tunneling-field-effect-transistor (TFET) has emerged as an alternative for conventional CMOS by enabling the supply voltage (VDD) scaling in ultra-low power, energy efficient computing, due to its sub-60 mV/decade sub-threshold slope (SS). Given its unique device characteristics such as the asymmetrical source/drain design induced uni-directional conduction, enhanced on-state Miller capacitance effect and steep switching at low voltages, TFET based circuit design requires strong interactions between the device-level and the circuit-level to explore the performance benefits, with certain modifications of the conventional CMOS circuits to achieve the functionality and optimal energy efficiency. Because TFET operates at low supply voltage range (VDD<0.5V) to outperform CMOS, reliability issues can have profound impact on the circuit design from the practical application perspective. In this review paper, we present recent development on Tunnel FET device design, and modeling technique for circuit implementation and performance benchmarking. We focus on the reliability issues such as soft-error, electrical noise and process variation, and their impact on TFET based circuit performance compared to sub-threshold CMOS. Analytical models of electrical noise and process variation are also discussed for circuit-level simulation.
AB - Tunneling-field-effect-transistor (TFET) has emerged as an alternative for conventional CMOS by enabling the supply voltage (VDD) scaling in ultra-low power, energy efficient computing, due to its sub-60 mV/decade sub-threshold slope (SS). Given its unique device characteristics such as the asymmetrical source/drain design induced uni-directional conduction, enhanced on-state Miller capacitance effect and steep switching at low voltages, TFET based circuit design requires strong interactions between the device-level and the circuit-level to explore the performance benefits, with certain modifications of the conventional CMOS circuits to achieve the functionality and optimal energy efficiency. Because TFET operates at low supply voltage range (VDD<0.5V) to outperform CMOS, reliability issues can have profound impact on the circuit design from the practical application perspective. In this review paper, we present recent development on Tunnel FET device design, and modeling technique for circuit implementation and performance benchmarking. We focus on the reliability issues such as soft-error, electrical noise and process variation, and their impact on TFET based circuit performance compared to sub-threshold CMOS. Analytical models of electrical noise and process variation are also discussed for circuit-level simulation.
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U2 - 10.1016/j.microrel.2014.02.002
DO - 10.1016/j.microrel.2014.02.002
M3 - Article
AN - SCOPUS:84899981934
SN - 0026-2714
VL - 54
SP - 861
EP - 874
JO - Microelectronics Reliability
JF - Microelectronics Reliability
IS - 5
ER -
