Tunnel transistors for low power logic

S. Datta; R. Bijesh; H. Liu; D. Mohata; V. Narayanan

doi:10.1109/CSICS.2013.6659248

Tunnel transistors for low power logic

S. Datta, R. Bijesh, H. Liu, D. Mohata, V. Narayanan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

27 Scopus citations

Abstract

Tunnel transistor (TFET) as steep slope device to enable supply voltage scaling is explored at the device level as well as circuit level. Hetero-junction TFET is demonstrated with high drive current and high on-off current ratio. Hetero-junction TFETs with scaled device geometry outperform Si FINFET at V_cc < 0.3V. Design considerations of TFET based circuits for logic applications are investigated and performance benchmarked with Si FinFET technology.

Original language	English (US)
Title of host publication	2013 IEEE Compound Semiconductor Integrated Circuit Symposium
Subtitle of host publication	Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013 - Technical Digest 2013
DOIs	https://doi.org/10.1109/CSICS.2013.6659248
State	Published - Nov 8 2013
Event	2013 35th IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013 - Monterey, CA, United States Duration: Oct 13 2013 → Oct 16 2013

Publication series

Name	Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
ISSN (Print)	1550-8781

Other

Other	2013 35th IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013
Country/Territory	United States
City	Monterey, CA
Period	10/13/13 → 10/16/13

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Condensed Matter Physics
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/CSICS.2013.6659248

Cite this

Datta, S., Bijesh, R., Liu, H., Mohata, D., & Narayanan, V. (2013). Tunnel transistors for low power logic. In 2013 IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013 - Technical Digest 2013 Article 6659248 (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC). https://doi.org/10.1109/CSICS.2013.6659248

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title = "Tunnel transistors for low power logic",

abstract = "Tunnel transistor (TFET) as steep slope device to enable supply voltage scaling is explored at the device level as well as circuit level. Hetero-junction TFET is demonstrated with high drive current and high on-off current ratio. Hetero-junction TFETs with scaled device geometry outperform Si FINFET at Vcc < 0.3V. Design considerations of TFET based circuits for logic applications are investigated and performance benchmarked with Si FinFET technology.",

author = "S. Datta and R. Bijesh and H. Liu and D. Mohata and V. Narayanan",

year = "2013",

month = nov,

day = "8",

doi = "10.1109/CSICS.2013.6659248",

language = "English (US)",

isbn = "9781479905836",

series = "Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC",

booktitle = "2013 IEEE Compound Semiconductor Integrated Circuit Symposium",

note = "2013 35th IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013 ; Conference date: 13-10-2013 Through 16-10-2013",

}

Datta, S, Bijesh, R, Liu, H, Mohata, D & Narayanan, V 2013, Tunnel transistors for low power logic. in 2013 IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013 - Technical Digest 2013., 6659248, Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC, 2013 35th IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013, Monterey, CA, United States, 10/13/13. https://doi.org/10.1109/CSICS.2013.6659248

Tunnel transistors for low power logic. / Datta, S.; Bijesh, R.; Liu, H. et al.
2013 IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013 - Technical Digest 2013. 2013. 6659248 (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Tunnel transistors for low power logic

AU - Datta, S.

AU - Bijesh, R.

AU - Liu, H.

AU - Mohata, D.

AU - Narayanan, V.

PY - 2013/11/8

Y1 - 2013/11/8

N2 - Tunnel transistor (TFET) as steep slope device to enable supply voltage scaling is explored at the device level as well as circuit level. Hetero-junction TFET is demonstrated with high drive current and high on-off current ratio. Hetero-junction TFETs with scaled device geometry outperform Si FINFET at Vcc < 0.3V. Design considerations of TFET based circuits for logic applications are investigated and performance benchmarked with Si FinFET technology.

AB - Tunnel transistor (TFET) as steep slope device to enable supply voltage scaling is explored at the device level as well as circuit level. Hetero-junction TFET is demonstrated with high drive current and high on-off current ratio. Hetero-junction TFETs with scaled device geometry outperform Si FINFET at Vcc < 0.3V. Design considerations of TFET based circuits for logic applications are investigated and performance benchmarked with Si FinFET technology.

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U2 - 10.1109/CSICS.2013.6659248

DO - 10.1109/CSICS.2013.6659248

M3 - Conference contribution

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SN - 9781479905836

T3 - Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC

BT - 2013 IEEE Compound Semiconductor Integrated Circuit Symposium

T2 - 2013 35th IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013

Y2 - 13 October 2013 through 16 October 2013

ER -

Datta S, Bijesh R, Liu H, Mohata D, Narayanan V. Tunnel transistors for low power logic. In 2013 IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013 - Technical Digest 2013. 2013. 6659248. (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC). doi: 10.1109/CSICS.2013.6659248

Tunnel transistors for low power logic

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