Ultra low power circuit design using tunnel FETs

Ravindhiran Mukundrajan; Matthew Cotter; Vinay Saripalli; Mary Jane Irwin; Suman Datta; Vijaykrishnan Narayanan

doi:10.1109/ISVLSI.2012.70

Ultra low power circuit design using tunnel FETs

Ravindhiran Mukundrajan
, Matthew Cotter
, Vinay Saripalli
, Mary Jane Irwin
, Suman Datta
, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

37 Scopus citations

Abstract

The proliferation of ubiquitous and mobile computing systems has created a new segment in the design space where energy efficiency is the most critical design parameter. With the end user expecting more functionality from these types of systems, there is a pressing need to evaluate emerging technologies that can overcome the limitations of CMOS. This work evaluates the potential of one such prospective MOSFET replacement device - the Tunnel FET (TFET). Novel circuit designs are presented to overcome unique design challenges posed by TFETs. The impacts of the proposed design techniques are characterized and a sparse prefix tree adder employing the proposed designs is presented. A considerable improvement in delay and significant reduction in energy is observed due to the combined impact of circuit and technology co-exploration.

Original language	English (US)
Title of host publication	Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Pages	153-158
Number of pages	6
DOIs	https://doi.org/10.1109/ISVLSI.2012.70
State	Published - 2012
Event	2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012 - Amherst, MA, United States Duration: Aug 19 2012 → Aug 21 2012

Publication series

Name	Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012

Other

Other	2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Country/Territory	United States
City	Amherst, MA
Period	8/19/12 → 8/21/12

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/ISVLSI.2012.70

Cite this

Mukundrajan, R., Cotter, M., Saripalli, V., Irwin, M. J., Datta, S., & Narayanan, V. (2012). Ultra low power circuit design using tunnel FETs. In Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012 (pp. 153-158). Article 6296465 (Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012). https://doi.org/10.1109/ISVLSI.2012.70

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title = "Ultra low power circuit design using tunnel FETs",

abstract = "The proliferation of ubiquitous and mobile computing systems has created a new segment in the design space where energy efficiency is the most critical design parameter. With the end user expecting more functionality from these types of systems, there is a pressing need to evaluate emerging technologies that can overcome the limitations of CMOS. This work evaluates the potential of one such prospective MOSFET replacement device - the Tunnel FET (TFET). Novel circuit designs are presented to overcome unique design challenges posed by TFETs. The impacts of the proposed design techniques are characterized and a sparse prefix tree adder employing the proposed designs is presented. A considerable improvement in delay and significant reduction in energy is observed due to the combined impact of circuit and technology co-exploration.",

author = "Ravindhiran Mukundrajan and Matthew Cotter and Vinay Saripalli and Irwin, \{Mary Jane\} and Suman Datta and Vijaykrishnan Narayanan",

year = "2012",

doi = "10.1109/ISVLSI.2012.70",

language = "English (US)",

isbn = "9780769547671",

series = "Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012",

pages = "153--158",

booktitle = "Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012",

}

Mukundrajan, R, Cotter, M, Saripalli, V, Irwin, MJ, Datta, S & Narayanan, V 2012, Ultra low power circuit design using tunnel FETs. in Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012., 6296465, Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, pp. 153-158, 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, Amherst, MA, United States, 8/19/12. https://doi.org/10.1109/ISVLSI.2012.70

Ultra low power circuit design using tunnel FETs. / Mukundrajan, Ravindhiran; Cotter, Matthew; Saripalli, Vinay et al.
Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012. 2012. p. 153-158 6296465 (Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

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AU - Mukundrajan, Ravindhiran

AU - Cotter, Matthew

AU - Saripalli, Vinay

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AU - Narayanan, Vijaykrishnan

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AB - The proliferation of ubiquitous and mobile computing systems has created a new segment in the design space where energy efficiency is the most critical design parameter. With the end user expecting more functionality from these types of systems, there is a pressing need to evaluate emerging technologies that can overcome the limitations of CMOS. This work evaluates the potential of one such prospective MOSFET replacement device - the Tunnel FET (TFET). Novel circuit designs are presented to overcome unique design challenges posed by TFETs. The impacts of the proposed design techniques are characterized and a sparse prefix tree adder employing the proposed designs is presented. A considerable improvement in delay and significant reduction in energy is observed due to the combined impact of circuit and technology co-exploration.

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BT - Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012

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ER -

Ultra low power circuit design using tunnel FETs

Abstract

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Other

UN SDGs

All Science Journal Classification (ASJC) codes

Access to Document

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