Unifying carry-sum and signed-digit number representations for low power

Historically, signed-digit adders have been thought of as being logically very complicated to implement, while carry-save adders have been considered to be fast, low power and easy to implement. While the latter is true, the former is a misconception. We show that for every integer k≥1, it is possible to build a network of radix-2^k signed-digit adders having the same logical complexity and hence the same area, delay and power consumption as a network of k-bit carry-sum adders (where, a 1-bit carry-sum adder is a carry-save adder). We also study the power and delay tradeoffs involved in using a network of carry-save and signed-digit adders for adding multiple operands when compared to a fast two's-complement adder and show that it always consumes less power. However, when the number of operands is large (>26), a tree of fast carry-lookahead adders was found to be faster.