Using truncated multipliers in DCT and IDCT hardware accelerators

E. George Walters, Mark G. Arnold, Michael J. Schulte

Research output: Contribution to journalConference articlepeer-review

13 Scopus citations


Truncated multipliers offer significant improvements in area, delay, and power. However, little research has been done on their use in actual applications, probably due to concerns about the computational errors they introduce. This paper describes a software tool used for simulating the use of truncated multipliers in DCTS and IDCT hardware accelerators. Images that have been compressed and decompressed by DCT and IDCT accelerators using truncated multipliers are presented. In accelerators based on Chen's algorithm (256 multiplies per 8 × 8 block for DCT, 224 multiplies per block for IDCT), there is no visble difference between images reconstructed using truncated multipliers with 55% of the multiplication matrix eliminated and images reconstructed using standard multipliers with the same operand lengths and intermediate precision.

Original languageEnglish (US)
Pages (from-to)573-584
Number of pages12
JournalProceedings of SPIE - The International Society for Optical Engineering
StatePublished - 2003
EventAdvanced Signal Processing Algorithms, Architectures, and Implementations - San Diego, USA, United States
Duration: Aug 6 2003Aug 8 2003

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering


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