TY - JOUR
T1 - Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances
AU - Liang, Yuhua
AU - Zhu, Zhangming
AU - Li, Xueqing
AU - Gupta, Sumeet Kumar
AU - Datta, Suman
AU - Narayanan, Vijaykrishnan
N1 - Funding Information:
Manuscript received March 13, 2019; revised June 24, 2019; accepted July 28, 2019. Date of publication September 13, 2019; date of current version November 22, 2019. This work was supported in part by the National Science Foundation of China under Grant 61604111, Grant 61874066, and Grant 61720106013; in part by the Fundamental Research Funds for the Central Universities under Grant JBX171104; in part by the Beijing Innovation Center for Future Chip; and in part by the SRC JUMP Center on Research on Intelligent Storage and Processing-In-Memory. (Corresponding authors: Zhangming Zhu; Vijaykrishnan Narayanan.) Y. Liang and Z. Zhu are with the Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an 710071, China (e-mail: [email protected]; [email protected]).
Publisher Copyright:
© 1993-2012 IEEE.
PY - 2019/12
Y1 - 2019/12
N2 - Negative-capacitance FETs (NCFETs) are a promising candidate for low-power circuits with intrinsic features, e.g., the steep switching slope. Prior works have shown potential for enabling low-power digital logic and memory design with NCFETs. Yet, it is still not quite clear how to harness these new features of NCFETs for analog functionalities. This article provides more insights into the circuit design space with new device characteristics and investigates its deployment in analog circuits, specifically, time-domain analog-to-digital converters (ADCs) and phase-locked loops (PLLs). We propose and optimize a novel digital-based clocked comparator and a capacitor-based voltage-to-time converter (VTC), which are essential building blocks in ADCs and PLLs. Evaluation results show beyond-FinFET comparison speed and enhanced linearity for the proposed NCFET-based clocked comparator and VTC, respectively. Such improvement is achieved by exploiting the steeper slope and increased output impedance of NCFETs. More details on design details and a discussion are provided in this article.
AB - Negative-capacitance FETs (NCFETs) are a promising candidate for low-power circuits with intrinsic features, e.g., the steep switching slope. Prior works have shown potential for enabling low-power digital logic and memory design with NCFETs. Yet, it is still not quite clear how to harness these new features of NCFETs for analog functionalities. This article provides more insights into the circuit design space with new device characteristics and investigates its deployment in analog circuits, specifically, time-domain analog-to-digital converters (ADCs) and phase-locked loops (PLLs). We propose and optimize a novel digital-based clocked comparator and a capacitor-based voltage-to-time converter (VTC), which are essential building blocks in ADCs and PLLs. Evaluation results show beyond-FinFET comparison speed and enhanced linearity for the proposed NCFET-based clocked comparator and VTC, respectively. Such improvement is achieved by exploiting the steeper slope and increased output impedance of NCFETs. More details on design details and a discussion are provided in this article.
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U2 - 10.1109/TVLSI.2019.2932268
DO - 10.1109/TVLSI.2019.2932268
M3 - Article
AN - SCOPUS:85072528472
SN - 1063-8210
VL - 27
SP - 2855
EP - 2860
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 12
M1 - 8836084
ER -