Utilizing self-assembled multilayers in lithographic processing for nanostructure fabrication: Initial evaluation of the electrical integrity of nanogaps

M. E. Anderson; Charan Srinivasan; Raviprakesh Jayaraman; P. S. Weiss; M. W. Horn

doi:10.1016/j.mee.2005.01.003

Utilizing self-assembled multilayers in lithographic processing for nanostructure fabrication: Initial evaluation of the electrical integrity of nanogaps

M. E. Anderson, Charan Srinivasan, Raviprakesh Jayaraman, P. S. Weiss, M. W. Horn

Research output: Contribution to journal › Conference article › peer-review

13 Scopus citations

Abstract

We apply self-assembly to form multilayers on gold structures formed by lithographic techniques to create patterns with spacings in the 10-100 nm regime. Controlled placement and thickness of these multilayers form "molecular ruler" resists to tailor spacings accurately between lithographically defined structures. We report on recent results both in designing and patterning complex nanostructures by combining photolithography and molecular rulers. After exposure, development, metal deposition, and lift-off of both the photoresist and molecular resist, the final product has secondary structures and gaps selectively oriented to create hierarchical nanostructures. The electrical integrity of the nanogaps formed using this process is evaluated for a variety of multilayer thicknesses and electrodes widths.

Original language	English (US)
Pages (from-to)	248-252
Number of pages	5
Journal	Microelectronic Engineering
Volume	78-79
Issue number	1-4
DOIs	https://doi.org/10.1016/j.mee.2005.01.003
State	Published - Mar 2005
Event	Proceedings of the 30th International Conference on Micro- and Nano-Engineering - Duration: Sep 19 2004 → Sep 22 2004

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics
Condensed Matter Physics
Surfaces, Coatings and Films
Electrical and Electronic Engineering

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10.1016/j.mee.2005.01.003

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abstract = "We apply self-assembly to form multilayers on gold structures formed by lithographic techniques to create patterns with spacings in the 10-100 nm regime. Controlled placement and thickness of these multilayers form {"}molecular ruler{"} resists to tailor spacings accurately between lithographically defined structures. We report on recent results both in designing and patterning complex nanostructures by combining photolithography and molecular rulers. After exposure, development, metal deposition, and lift-off of both the photoresist and molecular resist, the final product has secondary structures and gaps selectively oriented to create hierarchical nanostructures. The electrical integrity of the nanogaps formed using this process is evaluated for a variety of multilayer thicknesses and electrodes widths.",

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Utilizing self-assembled multilayers in lithographic processing for nanostructure fabrication: Initial evaluation of the electrical integrity of nanogaps. / Anderson, M. E.; Srinivasan, Charan; Jayaraman, Raviprakesh et al.
In: Microelectronic Engineering, Vol. 78-79, No. 1-4, 03.2005, p. 248-252.

Research output: Contribution to journal › Conference article › peer-review

TY - JOUR

T1 - Utilizing self-assembled multilayers in lithographic processing for nanostructure fabrication

T2 - Proceedings of the 30th International Conference on Micro- and Nano-Engineering

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AU - Srinivasan, Charan

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AB - We apply self-assembly to form multilayers on gold structures formed by lithographic techniques to create patterns with spacings in the 10-100 nm regime. Controlled placement and thickness of these multilayers form "molecular ruler" resists to tailor spacings accurately between lithographically defined structures. We report on recent results both in designing and patterning complex nanostructures by combining photolithography and molecular rulers. After exposure, development, metal deposition, and lift-off of both the photoresist and molecular resist, the final product has secondary structures and gaps selectively oriented to create hierarchical nanostructures. The electrical integrity of the nanogaps formed using this process is evaluated for a variety of multilayer thicknesses and electrodes widths.

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JO - Microelectronic Engineering

JF - Microelectronic Engineering

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Y2 - 19 September 2004 through 22 September 2004

ER -

Utilizing self-assembled multilayers in lithographic processing for nanostructure fabrication: Initial evaluation of the electrical integrity of nanogaps

Abstract

All Science Journal Classification (ASJC) codes

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