Process related variations are considered a major concern in emerging sub-65nm technologies. In this paper, we investigate the impact of process variations on different types of content addressable memories (CAM). As CAM structures are used in various on-chip structures such as caches and TLBs, understanding process variation impact of CAM structures is important. To gain insight on the relative importance of process variation effects, we also examine the effect of variability due to temperature and supply voltage changes. Our results show that the NAND-type CAM cells are more susceptible to failures as compared to NOR-type CAM cells. Finally, we propose an architectural technique to mitigate the performance degradation effects of process variation. The proposed technique yields an average of 37.5% 25% and 12.5% reduction in CAM occupancy for caches with 25% 50% and 75% variation respectively, over SPEC 2000 CPU benchmarks as compared to a worst-case design in the presence of process variation.