TY - GEN
T1 - Variation-aware low-power buffer design
AU - Nicopoulos, Chrysostomos
AU - Yanamandra, Aditya
AU - Srinivasan, Suresh
AU - Vijaykrishnan, N.
AU - Irwin, Mary Jane
N1 - Funding Information:
Potential conflicts of interest. The following list is a reflection of what has been reported to the IDSA. In order to provide thorough transparency, the IDSA requires full disclosure of all relationships, regardless of relevancy to the guideline topic. Evaluation of such relationships as potential conflicts of interest is determined by a review process that includes assessment by the SPGC chair, the SPGC liaison to the development panel, the Board of Directors liaison to the SPGC, and, if necessary, the Conflict of Interest Task Force of the board. This assessment of disclosed relationships for possible conflict of interest is based on the relative weight of the financial relationship (ie, monetary amount) and the relevance of the relationship (ie, the degree to which an association might reasonably be interpreted by an independent observer as related to the topic or recommendation of consideration). The reader of these guidelines should be mindful of this when the list of disclosures is reviewed. R. A. has served as a subinvestigator on clinical trials funded by ViroPharma, Roche, and the CDC. A. B. has served as a subinves-tigator on clinical trials funded by Abbott, UCB, and Merck; served as a consultant to Dyax, Cubist, and Nutricia; received speaking fees from Merck; and received a writing honorarium from Up-To-Date, Inc. E. G. D. has served as a consultant with GlaxoSmithKline and received a grant from Pfizer. I. K. has received research funding from Amino Up Chemical. H. K. has received funding from Pfizer for a clinical trial. M. L. has served as a consultant for Merck, MedImmune, and GlaxoSmithKline; has received honoraria and patent license from Merck; is on an adjudication committee for GlaxoS-mithKline; and participates in research studies with Sanofi Pasteur, GlaxoS-mithKline, and Merck. P. L. has served as a consultant to ViroPharma, Vical, Clinigen, Astellas Pharma, and Pfizer; served as an investigator for ViroPhar-ma, Astellas Pharma, Pfizer, and Merck; and chaired a Data and Safety Monitoring Board for AiCuris. No conflicts: G. A., L. R., S. D., M. T., L. S., and E. W. All other authors report no potential conflicts.
PY - 2007
Y1 - 2007
N2 - Process Variation (PV) is a consequence of manufacturing imperfections, which may lead to degraded performance or higher leakage power. In this paper, we focus on the design of an intelligent buffer that logically reorders the entries in FIFO buffer to minimize overall leakage power consumption. The buffer architecture, called IntelliBuffer, has been designed and evaluated in 90 nm and 32 nm CMOS technology. Our synthesized results show that our proposed design is as fast as a conventional buffer structure, while providing the ability to reduce power consumption significantly. When our buffer was used in a Network-on-Chip (NoC) implementation, we obtained 24% leakage savings at 90 nm, and savings of 28% at 32 nm. To further validate the efficacy of our proposed design, we incorporated IntelliBuffer into ViChaR, a recently introduced dynamic buffer management system for NoC routers. Experimental results indicate a marked reduction in ViChaR's leakage power consumption (21% at 90 nm) when IntelliBuffer is employed.
AB - Process Variation (PV) is a consequence of manufacturing imperfections, which may lead to degraded performance or higher leakage power. In this paper, we focus on the design of an intelligent buffer that logically reorders the entries in FIFO buffer to minimize overall leakage power consumption. The buffer architecture, called IntelliBuffer, has been designed and evaluated in 90 nm and 32 nm CMOS technology. Our synthesized results show that our proposed design is as fast as a conventional buffer structure, while providing the ability to reduce power consumption significantly. When our buffer was used in a Network-on-Chip (NoC) implementation, we obtained 24% leakage savings at 90 nm, and savings of 28% at 32 nm. To further validate the efficacy of our proposed design, we incorporated IntelliBuffer into ViChaR, a recently introduced dynamic buffer management system for NoC routers. Experimental results indicate a marked reduction in ViChaR's leakage power consumption (21% at 90 nm) when IntelliBuffer is employed.
UR - http://www.scopus.com/inward/record.url?scp=50249179684&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=50249179684&partnerID=8YFLogxK
U2 - 10.1109/ACSSC.2007.4487459
DO - 10.1109/ACSSC.2007.4487459
M3 - Conference contribution
AN - SCOPUS:50249179684
SN - 9781424421107
T3 - Conference Record - Asilomar Conference on Signals, Systems and Computers
SP - 1402
EP - 1406
BT - Conference Record of the 41st Asilomar Conference on Signals, Systems and Computers, ACSSC
T2 - 41st Asilomar Conference on Signals, Systems and Computers, ACSSC
Y2 - 4 November 2007 through 7 November 2007
ER -