TY - GEN
T1 - Vertical 2T-nC FeRAM Demonstration
T2 - 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025
AU - Deng, Shan
AU - Howe, John
AU - Ma, Sizhe
AU - Tauki, Sadik Yasir
AU - Zhao, Zijian
AU - Duan, Jiahui
AU - Lee, Yu Shan
AU - Qin, Yixin
AU - Joshi, Rajiv
AU - Kampfe, Thomas
AU - Gong, Xiao
AU - Narayanan, Vijaykrishnan
AU - Ni, Kai
N1 - Publisher Copyright:
© 2025 JSAP.
PY - 2025
Y1 - 2025
N2 - In this work, we demonstrate a vertical 2T-nC FeRAM with a back-end-of-line (BEOL) read transistor (TR) for 4 F2 string and propose a selector design to mitigate polarization disturb in passive capacitor crossbar arrays. Key contributions include: 1) successful integration and operation composed of a Si MOSFET write transistor (TW), 3-layer cylindrical ferroelectric capacitors, and Si-doped In2O3 BEOL TR, demonstrating the feasibility of 4 F2 2 T-nC string; 2) introducing nonlinearity into the capacitor stack to suppress ferroelectric voltage drop under inhibition biases while maintaining sufficient write voltage, reducing disturbance; 3)modeling and experimental validation of inserting a metalsemiconductor (a-Si)-metal (MSM) selector into the capacitor in mitigating the disturb, particularly achieving 9x reduction of disturb after 106 cycles in the VW/ 2 scheme.
AB - In this work, we demonstrate a vertical 2T-nC FeRAM with a back-end-of-line (BEOL) read transistor (TR) for 4 F2 string and propose a selector design to mitigate polarization disturb in passive capacitor crossbar arrays. Key contributions include: 1) successful integration and operation composed of a Si MOSFET write transistor (TW), 3-layer cylindrical ferroelectric capacitors, and Si-doped In2O3 BEOL TR, demonstrating the feasibility of 4 F2 2 T-nC string; 2) introducing nonlinearity into the capacitor stack to suppress ferroelectric voltage drop under inhibition biases while maintaining sufficient write voltage, reducing disturbance; 3)modeling and experimental validation of inserting a metalsemiconductor (a-Si)-metal (MSM) selector into the capacitor in mitigating the disturb, particularly achieving 9x reduction of disturb after 106 cycles in the VW/ 2 scheme.
UR - https://www.scopus.com/pages/publications/105012168011
UR - https://www.scopus.com/pages/publications/105012168011#tab=citedBy
U2 - 10.23919/VLSITechnologyandCir65189.2025.11074964
DO - 10.23919/VLSITechnologyandCir65189.2025.11074964
M3 - Conference contribution
AN - SCOPUS:105012168011
T3 - Digest of Technical Papers - Symposium on VLSI Technology
BT - 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 8 June 2025 through 12 June 2025
ER -