TY - JOUR
T1 - VFAB
T2 - A novel 2-stage STTRAM sensing using voltage feedback and boosting
AU - Motaman, Seyedhamidreza
AU - Ghosh, Swaroop
AU - Kulkarni, Jaydeep P.
N1 - Publisher Copyright:
© 2004-2012 IEEE.
PY - 2018/6
Y1 - 2018/6
N2 - Spin-torque-transfer RAM (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed. However, the process variation of STTRAM poses serious challenge to sensing. We propose a non-destructive and low-power sensing scheme that exploits a voltage feedback and boosting technique to develop large sense margin. Monte Carlo simulation results in ST Microelectronics 65-nm technology show that the proposed sensing circuit achieves 807-mV worst case sense margin on average, read access pass yield of σ in typical corner and × reduction in read power compared to conventional voltage sensing.
AB - Spin-torque-transfer RAM (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed. However, the process variation of STTRAM poses serious challenge to sensing. We propose a non-destructive and low-power sensing scheme that exploits a voltage feedback and boosting technique to develop large sense margin. Monte Carlo simulation results in ST Microelectronics 65-nm technology show that the proposed sensing circuit achieves 807-mV worst case sense margin on average, read access pass yield of σ in typical corner and × reduction in read power compared to conventional voltage sensing.
UR - https://www.scopus.com/pages/publications/85034251099
UR - https://www.scopus.com/inward/citedby.url?scp=85034251099&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2017.2766058
DO - 10.1109/TCSI.2017.2766058
M3 - Article
AN - SCOPUS:85034251099
SN - 1549-8328
VL - 65
SP - 1919
EP - 1928
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 6
ER -