VL-CDRAM: Variable Line Sized Cached DRAMs

Ananth Hegde; Vijaykrishnan Narayanan; Mahmut Kandemir; Mary Jane Irwin

doi:10.1109/CODESS.2003.1275272

VL-CDRAM: Variable Line Sized Cached DRAMs

Ananth Hegde
, Vijaykrishnan Narayanan
, Mahmut Kandemir
, Mary Jane Irwin

Research output: Contribution to conference › Paper › peer-review

6 Scopus citations

Abstract

Many of the current memory architectures embed a SRAM cache within the DRAM memory. These architectures exploit a wide internal data bus to transfer an entire DRAM row to the on-memory cache. However, applications exhibit a varying spatial locality across the different DRAM rows that are accessed and buffering the entire row may be wasteful. In order to adapt to the changing spatial locality, we propose a Variable Line size Cached DRAM (VL-CDRAM) that can buffer portions of an accessed DRAM row. Our evaluation shows that the proposed approach is effective in not only reducing the energy consumption but also in improving the performance across various memory configurations.

Original language	English (US)
Pages	132-137
Number of pages	6
DOIs	https://doi.org/10.1109/CODESS.2003.1275272
State	Published - Dec 1 2003
Event	First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003 - Newport Beach, CA, United States Duration: Oct 1 2003 → Oct 3 2003

Other

Other	First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003
Country/Territory	United States
City	Newport Beach, CA
Period	10/1/03 → 10/3/03

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Hardware and Architecture

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10.1109/CODESS.2003.1275272

Cite this

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title = "VL-CDRAM: Variable Line Sized Cached DRAMs",

abstract = "Many of the current memory architectures embed a SRAM cache within the DRAM memory. These architectures exploit a wide internal data bus to transfer an entire DRAM row to the on-memory cache. However, applications exhibit a varying spatial locality across the different DRAM rows that are accessed and buffering the entire row may be wasteful. In order to adapt to the changing spatial locality, we propose a Variable Line size Cached DRAM (VL-CDRAM) that can buffer portions of an accessed DRAM row. Our evaluation shows that the proposed approach is effective in not only reducing the energy consumption but also in improving the performance across various memory configurations.",

author = "Ananth Hegde and Vijaykrishnan Narayanan and Mahmut Kandemir and Irwin, \{Mary Jane\}",

year = "2003",

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doi = "10.1109/CODESS.2003.1275272",

language = "English (US)",

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T2 - First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003

AU - Hegde, Ananth

AU - Narayanan, Vijaykrishnan

AU - Kandemir, Mahmut

AU - Irwin, Mary Jane

PY - 2003/12/1

Y1 - 2003/12/1

N2 - Many of the current memory architectures embed a SRAM cache within the DRAM memory. These architectures exploit a wide internal data bus to transfer an entire DRAM row to the on-memory cache. However, applications exhibit a varying spatial locality across the different DRAM rows that are accessed and buffering the entire row may be wasteful. In order to adapt to the changing spatial locality, we propose a Variable Line size Cached DRAM (VL-CDRAM) that can buffer portions of an accessed DRAM row. Our evaluation shows that the proposed approach is effective in not only reducing the energy consumption but also in improving the performance across various memory configurations.

AB - Many of the current memory architectures embed a SRAM cache within the DRAM memory. These architectures exploit a wide internal data bus to transfer an entire DRAM row to the on-memory cache. However, applications exhibit a varying spatial locality across the different DRAM rows that are accessed and buffering the entire row may be wasteful. In order to adapt to the changing spatial locality, we propose a Variable Line size Cached DRAM (VL-CDRAM) that can buffer portions of an accessed DRAM row. Our evaluation shows that the proposed approach is effective in not only reducing the energy consumption but also in improving the performance across various memory configurations.

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UR - https://www.scopus.com/pages/publications/1142299885#tab=citedBy

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DO - 10.1109/CODESS.2003.1275272

M3 - Paper

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SP - 132

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Y2 - 1 October 2003 through 3 October 2003

ER -

VL-CDRAM: Variable Line Sized Cached DRAMs

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