VLSI Architectures for the Discrete Wavelet Transform

A class of VLSI architectures based on linear svs- tolic arrays, for computing the 1-D Discrete Wavelet Transform (DWT), is presented. The various architectures of this class differ only in the design of their routing networks, which could be systolic, semisystolic, or RAMbased. These architectures compute the Recursive Pyramid Algorithm, which is a reformulation of Mallat’s pyramid algorithm for the DWT. The DWT is computed in real time (running DWT), using just Nw(J—1) cells of storage, where Nwis the length of the filter and J is the number of octaves. They are ideally suited for single-chip implementation due to their practical I/O rate, small storage, and regularity. The N-point 1-D DWT is computed in 2 N cycles. The period can be reduced to N cycles by using Nwextra MAC’S. Our architectures are shown to be optimal in both computation time and in area. A utilization of 100% is achieved for the linear array. Extensions of our architecture for computing the M-band DWT are discussed. Also, two architectures for computing the 2-D DWT (separable case) are discussed. One of these architectures, based on a combination of systolic and parallel filters, computes the N2-point 2-D DWT, in real time, in N2 +N cycles, using 2N NW cells of storage.