TY - GEN
T1 - VLSI implementation of a 256×256 crossbar interconnection network
AU - Choi, Kyusun
AU - Adams, William S.
N1 - Copyright:
Copyright 2004 Elsevier B.V., All rights reserved.
PY - 1992
Y1 - 1992
N2 - Despite the fact that a crossbar interconnection network is desirable in parallel processing systems due to its flexibility of configuration and simplicity of control, many of the crossbars developed up to this time are small in size. In this paper, the analysis of VLSI layout size and signal delay of the previous crossbar circuits is presented. Also a circuit with better layout size and signal delay is presented in comparison. Based on the new circuit, the feasibility of the implementation is shown for a 256×256 crossbar on a 1 cm2 CMOS VLSI chip.
AB - Despite the fact that a crossbar interconnection network is desirable in parallel processing systems due to its flexibility of configuration and simplicity of control, many of the crossbars developed up to this time are small in size. In this paper, the analysis of VLSI layout size and signal delay of the previous crossbar circuits is presented. Also a circuit with better layout size and signal delay is presented in comparison. Based on the new circuit, the feasibility of the implementation is shown for a 256×256 crossbar on a 1 cm2 CMOS VLSI chip.
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M3 - Conference contribution
AN - SCOPUS:0026981687
SN - 0818626720
T3 - Proceedings of the International Conference on Parallel Processing
SP - 289
EP - 293
BT - Proceedings of the International Conference on Parallel Processing
PB - Publ by IEEE
T2 - Proceedings of the 6th International Parallel Processing Symposium
Y2 - 23 March 1992 through 26 March 1992
ER -