Watermarking of Quantum Circuits

Rupshali Roy, Swaroop Ghosh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Quantum circuits constitute Intellectual Property (IP) of the quantum developers and users, which needs to be protected from theft by adversarial agents e.g., the quantum cloud provider or a rogue adversary present in the cloud. This necessitates the exploration of low-overhead techniques applicable to near-term quantum devices, to trace the quantum circuits/algorithms' IP and their output. We present two such lightweight watermarking techniques to prove ownership in the event of an adversary cloning the circuit design. For the first technique a rotation gate is placed on ancilla qubits combined with other gate (s) at the output of the circuit. For the second method, a set of random gates are inserted in the middle of the circuit followed by its inverse, separated from the circuit by a barrier. These models are combined and applied on benchmark circuits and the circuit depth, 2-qubit gate count, probability of successful trials (PST) and probabilistic proof of authorship (PPA) are compared against the state-of-the-art. The PST is reduced by a miniscule 0.53% against the non-watermarked benchmarks and is up to 22.69% higher compared to existing techniques. The circuit depth has been reduced by up to 27.7% as against the state-of-the-art. The PPA is astronomically smaller than existing watermarks.

Original languageEnglish (US)
Title of host publicationProceedings of the 26th International Symposium on Quality Electronic Design, ISQED 2025
PublisherIEEE Computer Society
ISBN (Electronic)9798331509422
DOIs
StatePublished - 2025
Event26th International Symposium on Quality Electronic Design, ISQED 2025 - Hybrid, San Francisco, United States
Duration: Apr 23 2025Apr 25 2025

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Conference

Conference26th International Symposium on Quality Electronic Design, ISQED 2025
Country/TerritoryUnited States
CityHybrid, San Francisco
Period4/23/254/25/25

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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