TY - GEN
T1 - Watermarking of Quantum Circuits
AU - Roy, Rupshali
AU - Ghosh, Swaroop
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - Quantum circuits constitute Intellectual Property (IP) of the quantum developers and users, which needs to be protected from theft by adversarial agents e.g., the quantum cloud provider or a rogue adversary present in the cloud. This necessitates the exploration of low-overhead techniques applicable to near-term quantum devices, to trace the quantum circuits/algorithms' IP and their output. We present two such lightweight watermarking techniques to prove ownership in the event of an adversary cloning the circuit design. For the first technique a rotation gate is placed on ancilla qubits combined with other gate (s) at the output of the circuit. For the second method, a set of random gates are inserted in the middle of the circuit followed by its inverse, separated from the circuit by a barrier. These models are combined and applied on benchmark circuits and the circuit depth, 2-qubit gate count, probability of successful trials (PST) and probabilistic proof of authorship (PPA) are compared against the state-of-the-art. The PST is reduced by a miniscule 0.53% against the non-watermarked benchmarks and is up to 22.69% higher compared to existing techniques. The circuit depth has been reduced by up to 27.7% as against the state-of-the-art. The PPA is astronomically smaller than existing watermarks.
AB - Quantum circuits constitute Intellectual Property (IP) of the quantum developers and users, which needs to be protected from theft by adversarial agents e.g., the quantum cloud provider or a rogue adversary present in the cloud. This necessitates the exploration of low-overhead techniques applicable to near-term quantum devices, to trace the quantum circuits/algorithms' IP and their output. We present two such lightweight watermarking techniques to prove ownership in the event of an adversary cloning the circuit design. For the first technique a rotation gate is placed on ancilla qubits combined with other gate (s) at the output of the circuit. For the second method, a set of random gates are inserted in the middle of the circuit followed by its inverse, separated from the circuit by a barrier. These models are combined and applied on benchmark circuits and the circuit depth, 2-qubit gate count, probability of successful trials (PST) and probabilistic proof of authorship (PPA) are compared against the state-of-the-art. The PST is reduced by a miniscule 0.53% against the non-watermarked benchmarks and is up to 22.69% higher compared to existing techniques. The circuit depth has been reduced by up to 27.7% as against the state-of-the-art. The PPA is astronomically smaller than existing watermarks.
UR - https://www.scopus.com/pages/publications/105007523488
UR - https://www.scopus.com/inward/citedby.url?scp=105007523488&partnerID=8YFLogxK
U2 - 10.1109/ISQED65160.2025.11014402
DO - 10.1109/ISQED65160.2025.11014402
M3 - Conference contribution
AN - SCOPUS:105007523488
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
BT - Proceedings of the 26th International Symposium on Quality Electronic Design, ISQED 2025
PB - IEEE Computer Society
T2 - 26th International Symposium on Quality Electronic Design, ISQED 2025
Y2 - 23 April 2025 through 25 April 2025
ER -