When to forget: A system-level perspective on STT-RAMs

Karthik Swaminathan; Raghav Pisolkar; Cong Xu; Vijaykrishnan Narayanan

doi:10.1109/ASPDAC.2012.6164965

When to forget: A system-level perspective on STT-RAMs

Karthik Swaminathan, Raghav Pisolkar, Cong Xu, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Scopus citations

Abstract

The benefits of using STT-RAMs as an alternative to SRAMs are being examined in great detail. However their comparatively higher write latencies and energies continue to be roadblocks for migrating to MRAM based technology in memory hierarchies. In this paper, we present a novel method by which we demonstrate significant energy reduction in writing to the STT-RAM cell by relaxing its non-volatility property. We exploit this characteristic for optimizing system-level properties such as garbage collection. By categorizing the objects based on their lifetimes it is possible to tune the data retention time of the STT-RAM to minimize the write energy. Our scheme yielded 37% reduction in dynamic energy, 88% reduction in leakage and 85% improvement in the Energy-Delay Product over a corresponding SRAM based memory structure.

Original language	English (US)
Title of host publication	ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference
Pages	311-316
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2012.6164965
State	Published - 2012
Event	17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012 - Sydney, NSW, Australia Duration: Jan 30 2012 → Feb 2 2012

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other	17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012
Country/Territory	Australia
City	Sydney, NSW
Period	1/30/12 → 2/2/12

All Science Journal Classification (ASJC) codes

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/ASPDAC.2012.6164965

Cite this

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title = "When to forget: A system-level perspective on STT-RAMs",

abstract = "The benefits of using STT-RAMs as an alternative to SRAMs are being examined in great detail. However their comparatively higher write latencies and energies continue to be roadblocks for migrating to MRAM based technology in memory hierarchies. In this paper, we present a novel method by which we demonstrate significant energy reduction in writing to the STT-RAM cell by relaxing its non-volatility property. We exploit this characteristic for optimizing system-level properties such as garbage collection. By categorizing the objects based on their lifetimes it is possible to tune the data retention time of the STT-RAM to minimize the write energy. Our scheme yielded 37% reduction in dynamic energy, 88% reduction in leakage and 85% improvement in the Energy-Delay Product over a corresponding SRAM based memory structure.",

author = "Karthik Swaminathan and Raghav Pisolkar and Cong Xu and Vijaykrishnan Narayanan",

year = "2012",

doi = "10.1109/ASPDAC.2012.6164965",

language = "English (US)",

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series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "311--316",

booktitle = "ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference",

note = "17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012 ; Conference date: 30-01-2012 Through 02-02-2012",

}

Swaminathan, K, Pisolkar, R, Xu, C & Narayanan, V 2012, When to forget: A system-level perspective on STT-RAMs. in ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference., 6164965, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 311-316, 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, NSW, Australia, 1/30/12. https://doi.org/10.1109/ASPDAC.2012.6164965

When to forget: A system-level perspective on STT-RAMs. / Swaminathan, Karthik; Pisolkar, Raghav; Xu, Cong et al.
ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. 2012. p. 311-316 6164965 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - The benefits of using STT-RAMs as an alternative to SRAMs are being examined in great detail. However their comparatively higher write latencies and energies continue to be roadblocks for migrating to MRAM based technology in memory hierarchies. In this paper, we present a novel method by which we demonstrate significant energy reduction in writing to the STT-RAM cell by relaxing its non-volatility property. We exploit this characteristic for optimizing system-level properties such as garbage collection. By categorizing the objects based on their lifetimes it is possible to tune the data retention time of the STT-RAM to minimize the write energy. Our scheme yielded 37% reduction in dynamic energy, 88% reduction in leakage and 85% improvement in the Energy-Delay Product over a corresponding SRAM based memory structure.

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When to forget: A system-level perspective on STT-RAMs

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