Write-optimized STT-MRAM bit-cells using asymmetrically doped transistors

Sri Harsha Choday; Sumeet K. Gupta; Kaushik Roy

doi:10.1109/LED.2014.2358998

Write-optimized STT-MRAM bit-cells using asymmetrically doped transistors

Sri Harsha Choday, Sumeet K. Gupta, Kaushik Roy

Research output: Contribution to journal › Article › peer-review

23 Scopus citations

Abstract

Spin-transfer torque MRAM (STT-MRAM) is a potential candidate for replacing SRAMs in last level on-chip caches. However, it comes with high write power and oxide reliability issues due to large current required to achieve high speed switching. In this letter, we propose a technique to mitigate the conflict between write-ability and write power of STT MRAM using an access transistor with asymmetric doping at the source/drain terminals. Our technique achieves 35% write power reduction at iso-write speed. In addition, the maximum voltage drop across the tunnel barrier in the Magnetic Tunnel Junction reduces by 23% which improves its reliability.

Original language	English (US)
Article number	6915720
Pages (from-to)	1100-1102
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	35
Issue number	11
DOIs	https://doi.org/10.1109/LED.2014.2358998
State	Published - Nov 1 2014

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/LED.2014.2358998

Cite this

@article{6a4e7e130f21476a8d5bd903c11a74f7,

title = "Write-optimized STT-MRAM bit-cells using asymmetrically doped transistors",

abstract = "Spin-transfer torque MRAM (STT-MRAM) is a potential candidate for replacing SRAMs in last level on-chip caches. However, it comes with high write power and oxide reliability issues due to large current required to achieve high speed switching. In this letter, we propose a technique to mitigate the conflict between write-ability and write power of STT MRAM using an access transistor with asymmetric doping at the source/drain terminals. Our technique achieves 35% write power reduction at iso-write speed. In addition, the maximum voltage drop across the tunnel barrier in the Magnetic Tunnel Junction reduces by 23% which improves its reliability.",

author = "Choday, {Sri Harsha} and Gupta, {Sumeet K.} and Kaushik Roy",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.",

year = "2014",

month = nov,

day = "1",

doi = "10.1109/LED.2014.2358998",

language = "English (US)",

volume = "35",

pages = "1100--1102",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "11",

}

TY - JOUR

T1 - Write-optimized STT-MRAM bit-cells using asymmetrically doped transistors

AU - Choday, Sri Harsha

AU - Gupta, Sumeet K.

AU - Roy, Kaushik

PY - 2014/11/1

Y1 - 2014/11/1

N2 - Spin-transfer torque MRAM (STT-MRAM) is a potential candidate for replacing SRAMs in last level on-chip caches. However, it comes with high write power and oxide reliability issues due to large current required to achieve high speed switching. In this letter, we propose a technique to mitigate the conflict between write-ability and write power of STT MRAM using an access transistor with asymmetric doping at the source/drain terminals. Our technique achieves 35% write power reduction at iso-write speed. In addition, the maximum voltage drop across the tunnel barrier in the Magnetic Tunnel Junction reduces by 23% which improves its reliability.

AB - Spin-transfer torque MRAM (STT-MRAM) is a potential candidate for replacing SRAMs in last level on-chip caches. However, it comes with high write power and oxide reliability issues due to large current required to achieve high speed switching. In this letter, we propose a technique to mitigate the conflict between write-ability and write power of STT MRAM using an access transistor with asymmetric doping at the source/drain terminals. Our technique achieves 35% write power reduction at iso-write speed. In addition, the maximum voltage drop across the tunnel barrier in the Magnetic Tunnel Junction reduces by 23% which improves its reliability.

UR - http://www.scopus.com/inward/record.url?scp=84908367521&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84908367521&partnerID=8YFLogxK

U2 - 10.1109/LED.2014.2358998

DO - 10.1109/LED.2014.2358998

M3 - Article

AN - SCOPUS:84908367521

SN - 0741-3106

VL - 35

SP - 1100

EP - 1102

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 11

M1 - 6915720

ER -

Write-optimized STT-MRAM bit-cells using asymmetrically doped transistors

Abstract

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this