Write-optimized STT-MRAM bit-cells using asymmetrically doped transistors

Spin-transfer torque MRAM (STT-MRAM) is a potential candidate for replacing SRAMs in last level on-chip caches. However, it comes with high write power and oxide reliability issues due to large current required to achieve high speed switching. In this letter, we propose a technique to mitigate the conflict between write-ability and write power of STT MRAM using an access transistor with asymmetric doping at the source/drain terminals. Our technique achieves 35% write power reduction at iso-write speed. In addition, the maximum voltage drop across the tunnel barrier in the Magnetic Tunnel Junction reduces by 23% which improves its reliability.